semicustom products utr 0.8 m gate array family preliminary data sheet jan. 2000 features q up to 200,000 usable equivalent gates q clock rates up to 180 mhz q advanced 0.8 m radiation-hardened silicon gate cmos q operating voltage of 5v q qml class q & v compliant q designed specifically for high reliability applications q radiation-hardened to 1.0e6 rads(si) total dose (functional) and seu-immune cells to less than 1.0e-10 errors/bit-day q jtag (ieee 1149.1) boundary-scan registers built into i/o cells q low noise package technology for high speed circuits q design support using mentor graphics?, synopsys tm and vhdl tools on hp? and sun? workstations q standard microcircuit drawing pending product description the high-performance utr 0.8 m gate array family features densities of up to 200,000 equivalent gates and is avail- able in mil-prf-38535 qml q and v quality levels and radiation-hardened. for those designs requiring stringent radiation hardness, utr?s 0.8 m process employs a special processing module that enhances the total dose radiation hardness of the field and gate oxides while maintaining circuit density and reliability. in ad- dition, for both greater transient radiation-hardness and latchup immunity, the utr 0.8 m process is built on epitaxial substrate wafers. developed from utmc?s patented architectures, the utr 0.8 m array family uses a highly efficient continuous tran- sistor architecture for the internal cell construction. combined with state-of-the-art placement and routing tools, the utilization of available transistors is maximized using three lev- els of metal interconnect. the utr 0.8 m family of gate arrays is supported by an exten- sive cell library that includes ssi, msi, and 54xx equivalent functions, as well as, configurable ram and other megafunc- tions. utmc?s megacell library includes the following functions: intel 80c31? equivalent mil-std-1553 functions (brctm, rti, rtmp) mil-std-1750 microprocessor risc microcontroller configurable ram
2 table 1. gate densities notes: 1. the "r" denotes radiation-hardened. 2. based on nand2 equivalents. actual usable gate count is design-dependent. estimates reflect a mix of functions including ram. 3. includes five pins that may or may not be reserved for jtag boundary-scan, depending on user requirements. 4. reserved for dedicated v dd /v ss and v ddq /v ssq . low-noise device and package solutions the utr 0.8 m output drivers feature programmable slew rate control for minimizing noise and switching transients. this fea- ture allows the user to optimize edge characteristics to match system requirements. separate on-chip power and ground buses are provided for internal cells and output drivers which further isolate internal design circuitry from switching noise. in addition, utmc offers advanced low-noise package technol- ogy with multi-layer, co-fired ceramic construction featuring built-in isolated power and ground planes. these planes provide lower overall resistance/inductance through power and ground paths which minimize voltage drops during periods of heavy switching. these isolated planes also help sustain supply volt- age during dose rate events, thus preventing rail span collapse. flatpacks are available with up to 304 leads; pgas are available with up to 280 leads. utmc?s flatpacks feature a non-conduc- tive tie bar that helps maintain lead integrity through test and handling operations. in addition to the packages listed in table 2, utmc offers custom package development and package tool- ing modification services for individual requirements. table 2. packages notes: 1. the number of device i/o pads available may be restricted by the selected package. 2. pga packages have one additional non-connected index pin (i.e., 144 + 1 index pin = 145 total package pins for the 144 pga). contact utmc for specific package drawings. device part numbers 1 equivalent usable gates 2 signal i/o 3 power & ground pads 4 utr25 5,000 - 25,000 175 40 utr35 35,000 175 40 utr50 50,000 175 40 utr75 75,000 256 80 UTR100 125,000 256 80 utr150 150,000 256 80 utr200 200,000 256 80 package type/leadcount 1 utr25 utr35 utr50 utr75 UTR100 utr150 utr200 flatpack 84 x x x 132 x x x 172 x x x x x x x 196 x x x x x x x 224 x x x x 256 x x x x 304 x x x x pga 2 84 x x x 120 x x x x 144 x x x 208 x x x x x x x 280 x x x x
3 extensive cell library the utr 0.8 m family of gate arrays is supported by an extensive cell library that includes ssi, msi, and 54xx-equivalent func- tions, as well as, ram and other megafunctions. user- selectable options for cell configurations include scan for all register elements, as well as output drive strength. utmc?s megacell library includes the following functions: intel? 80c31 equivalent mil-std-1553 functions (bcrtm, rti, rtmp) mil-std-1750 microprocessor standard microprocessor peripheral functions configurable ram refer to utmc?s utr 0.8 m design manual for complete cell listing and details. i/o buffers the utr 0.8 m gate array family offers up to 342 device pad locations (note: device pad availability is affected by package selection and pinout.) the i/o cells can be configured by the user to serve as input, output, bidirectional, three-state, or addi- tional power and ground pads. output drive options range from 2 to 8ma. to drive larger off-chip loads, output drivers can be combined in parallel to provide additional drive up to 12ma. other i/o buffer features and options include: slew rate control pull-up and pull-down resistors ttl, cmos, and schmitt levels built-in boundary-scan jtag boundary-scan the utr 0.8 m arrays include a test access port and boundary- scan architecture that conforms to the ieee standard 1149.1 (jtag). some of the benefits this capability offers include the following: allows easy test of complex assembled printed circuit boards can be used to gain access to and control internal scan paths can be used to initiate built-in self test clock driver distribution utmc design tools provide methods for balanced clock distri- bution that maximize drive capability and minimize relative clock skew between clocked devices. speed and performance utmc specializes in high-performance circuits designed to op- erate in harsh military and radiation environments. table 3 presents a sampling of typical cell delays. note that the propagation delay for a cmos device is a function of its fanout loading, supply voltage, operating temperature, and processing tolerance. in a radiation environment, additional per- formance variances must be considered. the utr 0.8 m simulation models account for all of these effects to accurately determine circuit performance for its particular set of use conditions. power dissipation each internal gate or i/o driver has an average power consump- tion based on its switching frequency and capacitive loading. the radiation-hardened processes exhibit power dissipation that is typical of cmos processes. for a rigorous power estimating methodology, refer to the utmc utr 0.8 m design manual or consult with a utmc applications engineer.
4 table 3. typical cell delays note: 1. all specifications in ns (typical). output load capacitance is 50pf. fanout loading for input buffers and gates is the equivalen t of two gate input loads. cell output transition propagation delay 1 internal gates inv1, inverter hl 0.26 lh 0.39 inv4, inverter 4x hl 0.14 lh 0.23 nand2, 2-input nand hl 0.35 lh 0.39 nor2, 2-input nor hl 0.25 lh 0.61 dff clk to q 1.53 latch enable to q 1.45 output buffers o8n19, cmos hl 3.22 lh 2.33 o4n10, ttl scan, 4ma hl 5.92 lh 4.01 otn10, ttl scan, 12ma hl 3.76 lh 3.14 input buffers icn19, cmos hl .597 lh .482 itn19, ttl hl .787 lh .735
5 asic design software using a combination of state-of-the-art third-party and propri- etary design tools, utmc delivers the cae support and capability to handle complex, high-performance asic designs from design concept through design verification and test. design creation utmc?s flexible design creation methodology supports high level design by providing utr 0.8 m cell libraries for synthesis. using mentor graphics and synopsys synthesis tools, a structural design can be created for verification in vital- compliant vhdl or the mentor graphics environment. utmc?s cell libraries also support automatic test program generation (atpg) to improve design testing. design analysis utmc?s design analysis tools check the integrity of the design and ensure that it can be manufactured in utmc processes. design analysis tools include : tools supported by utmc xdt s m ( e x t e r n a l d esign translation) through utmc?s xdt services, customers can convert an existing non-utmc design to utmc?s processes. the xdt tool is particularly useful for converting an fpga to a utmc radiation-hardened gate array. the xdt translation tools convert industry standard netlist formats and vendor libraries to utmc formats and libraries. industry standard netlist formats supported by utmc include: vhdl verilog hdl tm fpga source files (actel, altera, xilinx) edif third-party netlists supported by synopsys design analysis tool function logic rules checker makes sure the design meets connectivity rules tester rules checker makes sure the design can be tested on utmc testers design transfer tool allows accurate transfer of design data to utmc mentor graphics synopsys vhdl autologicii ? design compiler tm synopsys vss tm quicksimii ? vhdl compiler tm mentor graphics quick- hdl ? quickfault ii ? testsim tm cadence leapfrog ? quickgradeii ? verilog hdl compiler tm viewlogic vantage tm fastscan ? / flextest ? / dft advisor ? test compiler plus tm any vital- compliant vhdl tool
6 physical design using three layers of metal interconnect, utmc achieves optimized layouts that maximize speed of critical nets, overall chip performance, and design density up to 200,000 equivalent gates. test capability utmc supports all phases of test development from test stim- ulus generation through high-speed production test. this support includes atpg, fault simulation, and fault grading. scan design options are available on all utr 0.8 m storage ele- ments. in addition, all utr 0.8 m arrays feature jtag boundary- scan (per ieee standard 1149.1). automatic test program de- velopment capabilities handle large vector sets for use with utmc?s ltx/trillium micromasters, supporting high-speed testing (up to 80mhz with pin multiplexing). unparalleled quality and reliability utmc is dedicated to satisfying the demanding quality and reliability requirements of aerospace and defense systems sup- pliers. quality assurance and reliability programs are integrated into the entire manufacturing process with statistical process control (spc) fully implemented for all manufacturing opera- tions. these high quality standards have enabled utmc to offer product in accordance with: mil-prf-38535, qml q and v iso-9001 other enhanced reliability flows because of numerous product variations permitted with custom- er specific designs, much of the reliability testing is performed using a standard evaluation circuit (sec) and technology characterization vehicle (tcv). thus, utmc can assure high reliability prior to delivery of product to the customer. radiation hardened utmc incorporates radiation-hardening techniques in process design, design rules, array design, power distribution, and li- brary element design. all key radiation-hardening process parameters are controlled and monitored using statistical meth- ods and in-line testing. notes: 1. total dose co-60 testing is in accordance with mil-std-883, method 1019. data sheet electrical characteristics guaranteed to 1.0e6 rads(si). all post-radiation values measured at 25 c; i ddq post-rad limit = 4ma. 2. short pulse 20ns fwhm (full width, half maximum). 3. may be design dependent, seu limit based on standard evaluation circuit. 4. seu-hard flip-flop cell. non-hard flip-flop typical is 5e-8. parameter radiation hard notes total dose 1.0e6 rads(si) functional 1 dose rate upset 1.0e9 rads(si)/sec 2 dose rate survivability 1.0e12 rads(si)/sec 3 seu <1.0e-10 errors per cell- day 3,4 projected neutron fluence 1.0e14 n/sq cm latchup latchup-immune over specified use conditions
7 absolute maximum ratings 1 (referenced to v ss ) note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions symbol parameter limits v dd dc supply voltage -0.3 to 7.0v v i/o voltage on any pin -0.3v to v dd + 0.3 t stg storage temperature -65 to +150 c t j maximum junction temperature +175 c i lu latchup immunity + 150ma i i dc input current + 10ma t ls lead temperature (soldering 5 sec) +300 c symbol parameter limits v dd positive supply voltage 4.5 to 5.5v t c case temperature range -55 to +125c v in dc input voltage 0v to v dd
8 dc electrical characteristics (v dd = 5.0v + 10%; -55 c < t c < +125 c) symbol parameter condition min typ max unit v il low-level input voltage 1 ttl inputs cmos, osc inputs 0.8 .3v dd v v ih high-level input voltage 1 ttl inputs cmos, osc inputs 2.2 .7v dd v v t + schmitt trigger, positive going 1 threshold 4.0 v v t - schmitt trigger, negative going 1 threshold 1.0 v v h schmitt trigger, typical range of hysteresis 2 1.5 2.0 v i in input leakage current ttl, cmos, and schmitt inputs inputs with pull-down resistors inputs with pull-down resistors, osc inputs with pull-up resistors inputs with pull-up resistors, osc v in = v dd or v ss v in = v dd v in = v ss v in = v ss v in = v dd -1 +150 -10 -900 -10 1 +900 +10 -150 +10 m a v ol low-level output voltage 3 ttl half-drive buffer ttl single-drive buffer ttl double-drive buffer ttl triple-drive buffer * cmos outputs cmos outputs (optional) osc outputs i ol = 2.0ma i ol = 4.0ma i ol = 8.0ma i ol = 12.0ma i ol = 1.0 m a i ol = 100 m a i ol = 100 m a 0.4 0.4 0.4 0.4 0.05 0.25 1.0 v v oh high-level output voltage 3 ttl half-drive buffer ttl single-drive buffer ttl double-drive buffer ttl triple-drive buffer * cmos outputs cmos outputs (optional) osc outputs i oh = -2.0ma i oh = -4.0ma i oh = -8.0ma i oh = -12.0ma i oh = -1.0 m a i oh = -100 m a i oh = -100 m a 2.4 2.4 2.4 2.4 v dd -0.05 v dd -0.25 3.5 v
9 notes: * contact utmc prior to usage. 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input volta ge within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density < 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pf*mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. symbol parameter condition min typ max unit i oz three-state output leakage current ttl half-drive buffer ttl single-drive, cmos, osc buffers ttl double-drive buffer ttl triple-drive buffer * v o = v dd and v ss -5 -10 -20 -30 5 10 20 30 m a i os short-circuit output current 2 ,4 ttl half-drive buffer ttl single-drive, cmos, osc buffers ttl double-drive buffer ttl triple-drive buffer * v o = v dd and v ss -50 -100 -200 -300 50 100 200 300 ma i ddq quiescent supply current v dd = 5.5v 1 ma c in input capacitance 5 | = 1mhz @ 0v 12 pf c out output capacitance 5 ttl half-drive buffer ttl single-drive, cmos, osc buffers ttl double-drive buffer ttl triple-drive buffer * | = 1mhz @ 0v 11 12 14 22 pf c io bidirect i/o capacitance 5 ttl single-drive, cmos, osc buffers ttl double-drive buffer ttl triple-drive buffer * | = 1mhz @ 0v 13 15 23 pf
10 hp/apollo and hp-ux are registered trademarks of hewlett-packard, inc. intel is a registered trademark of intel corporation mentor, mentor graphics, autologic ii, quicksim ii, quickfault ii, quickhdl, quickgrade ii, fastscan, flextest and dft advisor a re registered trademarks of mentor graphics corporation sun is a registered trademark of sun microsystems, inc. verilog and leapfrog are registered trademarks of cadence design systems, inc. synopsys, design compiler, test compiler plus, vhdl compiler, verilog hdl compiler, testsim and vss are trademarks of synopsys, inc. vantage is a trademark of viewlogic
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